; Definitions common to all 68hc11e MCUs ; -------------------------------------- ; General Addresses ; CSREGS equ $1000 ; *default* base addr of control-register block ; for the on-chip devices OC_RAM equ $0000 ; *default* start addr of internal on-chip RAM OC_RAMSIZ equ 512 ; E-series OC_EEPROM equ $B600 ; start addr of internal on-chip EEPROM ; 68hc11e on-chip-device control-/status-registers ; ; These "addresses" are given as (8-bit) offsets relative to the base address of the control block, ; because that base address can be changed at runtime... PORTA equ $00 ; Port A data PIOC equ $02 PORTC equ $03 ; Port C data PORTB equ $04 ; Port B data (output only) PORTCL equ $05 ; Latched Port C data DDRC equ $07 ; Port C data-direction control PORTD equ $08 ; Port D data DDRD equ $09 ; Port D data-direction control PORTE equ $0A ; Port E digital data (input only) CFORC equ $0B ; Compare Force Register OC1M equ $0C ; OC1 Action Mask Register OC1D equ $0D ; OC1 Action Data Register TCNT equ $0E ; Timer Counter Register TIC1 equ $10 ; Input Capture 1 Register TIC2 equ $12 ; Input Capture 2 Register TIC3 equ $14 ; Input Capture 3 Register TOC1 equ $16 ; Output Compare 1 Register TOC2 equ $18 ; Output Compare 2 Register TOC3 equ $1A ; Output Compare 3 Register TOC4 equ $1C ; Output Compare 4 Register TOC5 equ $1E ; Output Compare 5 Register TCTL1 equ $20 ; Timer Control Register 1 TCTL2 equ $21 ; Timer Control Register 2 TMSK1 equ $22 ; Timer Interrupt Mask Register 2 TFLG1 equ $23 ; Timer Interrupt Flag Register 1 TMSK2 equ $24 ; Timer Interrupt Mask Register 2 TFLG2 equ $25 ; Timer Interrupt Flag Register 2 PACTL equ $26 ; Pulse Accumulator Control Register PACNT equ $27 ; Pulse Accumulator Count Register SPCR equ $28 ; SPI Control Register SPSR equ $29 ; SPI Status Register SPDR equ $2A ; SPI Data Register BAUD equ $2B ; SCI Baud Rate Control SCCR1 equ $2C ; SCI Control Register 1 SCCR2 equ $2D ; SCI Control Register 2 SCSR equ $2E ; SCI Status Register SCDR equ $2F ; SCI Data Register ADCTL equ $30 ; A/D Control Register ADR1 equ $31 ; A/D Result Register 1 ADR2 equ $32 ; A/D Result Register 2 ADR3 equ $33 ; A/D Result Register 3 ADR4 equ $34 ; A/D Result Register 4 BPROT equ $35 ; EEPROM Block Protect EPROG equ $36 ; EEPROM Programming Control Register ; for E18/E20 only; see PPROG. OPTION equ $39 ; General Options COPRST equ $3A ; COP Watchdog Reset PPROG equ $3B ; EPROM Programming Control Register ; also for EEPROM except on E18/E20. HPRIO equ $3C ; Highest Priority and Miscellaneous INIT equ $3D ; RAM and I/O mapping; ; also EEPROM mapping on E2/E20 CONFIG equ $3F ; static COP, ROM, and EEPROM Enables ; 1-bit masks for IC/OC enables and flags TMSK1 and TFLG1 IC3BM equ $01 IC2BM equ $02 IC1BM equ $04 IC4BM equ $08 OC5BM equ IC4BM OC4BM equ $10 OC3BM equ $20 OC2BM equ $40 OC1BM equ $80