=~=~=~=~=~=~=~=~=~=~=~= PuTTY log 2019.11.06 17:39:20 =~=~=~=~=~=~=~=~=~=~=~= Hardware Power ON TOD Watchdog 0,0> 0,0>@(#) POST 3.9.27 2000/08/18 11:19 0,1> 0,0>Copyright 2000 Sun Microsystems, Inc. All rights reserved. 0,1>@(#) POST 3.9.27 2000/08/18 11:19 0,0> SelfTest Initializing (Diag Level 10, ENV 0000ff00) IMPL 0011 MASK 11 0,1>Copyright 2000 Sun Microsystems, Inc. All rights reserved. 0,0>Board 0 CPU FPROM Test 0,1> SelfTest Initializing (Diag Level 10, ENV 00000000) IMPL 0011 MASK 11 0,0>Board 0 Basic CPU Test 0,0> Set CPU UPA Config and Init SDB Data 0,0>SRAM Mode = 22, Clock Mode = 4:1, PCON = 6b3, MCAP = 0 0,0>Board 0 MMU Enable Test 0,0> DMMU Init 0,0> IMMU Init 0,0> Mapping Selftest Enabling MMUs 0,0>Board 0 Ecache Test 0,0> Ecache Probe 0,0> Ecache Tags 0,1>Board 0 CPU FPROM Test 0,1>Board 0 Basic CPU Test 0,1> Set CPU UPA Config and Init SDB Data 0,1>SRAM Mode = 22, Clock Mode = 4:1, PCON = 6b3, MCAP = 0 0,1>Board 0 MMU Enable Test 0,1> DMMU Init 0,1> IMMU Init 0,1> Mapping Selftest Enabling MMUs 0,1>Board 0 Ecache Test 0,1> Ecache Probe 0,1> Ecache Tags 0,0> Ecache Quick Verify 0,1> Ecache Quick Verify 0,0> Ecache Init 0,1> Ecache Init 0,0> Ecache RAM 0,1> Ecache RAM 0,0> Ecache Address Line 0,0> Configure Ecache Limit 0,0>Ecache Size = 00100000, Limited to 00100000 0,0>Board 0 FPU Functional Test 0,0> FPU Enable 0,0>Board 0 Board Master Select Test 0,0> Selecting a Board Master 0,0>Board 0 FireHose Devices Test 0,1> Ecache Address Line 0,1> Configure Ecache Limit 0,1>Ecache Size = 00100000, Limited to 00100000 0,1>Board 0 FPU Functional Test 0,1> FPU Enable 0,1>Board 0 Board Master Select Test 0,1> Selecting a Board Master 0,0>Board 0 Address Controller Test 0,0> AC Initialization 0,0> AC DTAG Init 0,0>Board 0 Dual Tags Test 0,0> AC DTAG Init 0,0>Board 0 FireHose Controller Test 0,0> FHC Initialization 0,0>Board 0 JTAG Test 0,0> Verify System Board Scan Ring 0,0>Board 0 Centerplane Test 0,0> Centerplane Join 0,0>Setting JTAG Master 0,0>Clear JTAG Master 0,0>Board 0 Setup Cache Size Test 0,0> Setting Up Cache Size 0,0>Board 0 System Master Select Test 0,0> Setting System Master 0,0>POST Master Selected (JTAG,CENTRAL) 0,0>Board 16 Clock Board Test 0,0> Clock Board Initialization 0,0> Clock Board Temperature Check 0,0>Board 16 Clock Board Serial Ports Test 0,0>Board 16 NVRAM Devices Test 0,0> M48T59 (TOD) Init 0,0>Board 0 System Board Probe Test 0,0> Probing all CPU/Memory BDA 0,0> Probing System Boards 0,0> Probing CPU Module JTAG Rings 0,0>Setting System Clock Frequency 0,0>CPU Module mid 0 Checked in OK (speed code = 4) 0,0>CPU mid 1 Version=00170011.11000507 0,0>CPU Module mid 1 Checked in OK (speed code = 4) 0,0>CPU mid 8 Version=00170011.11000507 0,0>CPU Module mid 8 Checked in OK (speed code = 4) 0,0>CPU mid 9 Version=00170011.11000507 0,0>CPU Module mid 9 Checked in OK (speed code = 4) 0,0>CPU mid 10 Version=00170011.11000507 0,0>CPU Module mid 10 Checked in OK (speed code = 4) 0,0>CPU mid 11 Version=00170011.11000507 0,0>CPU Module mid 11 Checked in OK (speed code = 4) 0,0>CPU mid 12 Version=00170011.11000507 0,0>CPU Module mid 12 Checked in OK (speed code = 4) 0,0>CPU mid 13 Version=00170011.11000507 0,0>CPU Module mid 13 Checked in OK (speed code = 4) 0,0>CPU mid 14 Version=00170011.11000507 0,0>CPU Module mid 14 Checked in OK (speed code = 4) 0,0>CPU mid 15 Version=00170011.11000507 0,0>CPU Module mid 15 Checked in OK (speed code = 4) 0,0>CPU mid 16 Version=00170011.11000507 0,0>CPU Module mid 16 Checked in OK (speed code = 4) 0,0>CPU mid 17 Version=00170011.11000507 0,0>CPU Module mid 17 Checked in OK (speed code = 4) 0,0>CPU mid 18 Version=00170011.11000507 0,0>CPU Module mid 18 Checked in OK (speed code = 4) 0,0>CPU mid 19 Version=00170011.11000507 0,0>CPU Module mid 19 Checked in OK (speed code = 4) 0,0>CPU mid 22 Version=00170011.11000507 0,0>CPU Module mid 22 Checked in OK (speed code = 4) 0,0>CPU mid 23 Version=00170011.11000507 0,0>CPU Module mid 23 Checked in OK (speed code = 4) 0,0> ******** Clock Reset - retesting 0,0>System Frequency (MHz),fcpu=248, fmod=124, fsys=82, fgen=496 0,0> 0,0>@(#) POST 3.9.27 2000/08/18 11:19 0,1> 0,0>Copyright 2000 Sun Microsystems, Inc. All rights reserved. 0,1>@(#) POST 3.9.27 2000/08/18 11:19 0,0> SelfTest Initializing (Diag Level 40, ENV 0000ff80) IMPL 0011 MASK 11 0,1>Copyright 2000 Sun Microsystems, Inc. All rights reserved. 0,0>Board 0 CPU FPROM Test 0,1> SelfTest Initializing (Diag Level 40, ENV 0000ff80) IMPL 0011 MASK 11 0,0> CPU/Memory Board FPROM Checksum Test 0,1>Board 0 CPU FPROM Test 0,1> CPU/Memory Board FPROM Checksum Test 0,0>Board 0 Basic CPU Test 0,0> FPU Registers and Data Path Test 0,0> Instruction Cache Tag RAM Test 0,1>Board 0 Basic CPU Test 0,1> FPU Registers and Data Path Test 0,1> Instruction Cache Tag RAM Test 0,0> Instruction Cache Instruction RAM Test 0,1> Instruction Cache Instruction RAM Test 0,1> Instruction Cache Next Field RAM Test 0,0> Instruction Cache Next Field RAM Test 0,1> Instruction Cache Pre-decode RAM Test 0,0> Instruction Cache Pre-decode RAM Test 0,1> Data Cache RAM Test 0,0> Data Cache RAM Test 0,1> Data Cache Tags Test 0,1> DMMU Registers Access Test 0,1> DMMU TLB DATA RAM Access Test 0,1> DMMU TLB TAGS Access Test 0,1> IMMU Registers Access Test 0,1> IMMU TLB DATA RAM Access Test 0,1> IMMU TLB TAGS Access Test 0,1> Set CPU UPA Config and Init SDB Data 0,1>SRAM Mode = 22, Clock Mode = 3:1, PCON = 6b3, MCAP = 0 0,1>Board 0 MMU Enable Test 0,1> DMMU Init 0,1> IMMU Init 0,1> Mapping Selftest Enabling MMUs 0,1>Board 0 Ecache Test 0,1> Ecache Probe 0,1> Ecache Tags 0,0> Data Cache Tags Test 0,0> DMMU Registers Access Test 0,0> DMMU TLB DATA RAM Access Test 0,0> DMMU TLB TAGS Access Test 0,0> IMMU Registers Access Test 0,0> IMMU TLB DATA RAM Access Test 0,0> IMMU TLB TAGS Access Test 0,0> Set CPU UPA Config and Init SDB Data 0,0>SRAM Mode = 22, Clock Mode = 3:1, PCON = 6b3, MCAP = 0 0,0>Board 0 MMU Enable Test 0,0> DMMU Init 0,0> IMMU Init 0,0> Mapping Selftest Enabling MMUs 0,0>Board 0 Ecache Test 0,0> Ecache Probe 0,0> Ecache Tags 0,1> Ecache Quick Verify 0,0> Ecache Quick Verify 0,1> Ecache Init 0,1> Ecache RAM 0,1> Ecache 6N RAM Pattern Test 0,0> Ecache Init 0,1> Ecache Address Line 0,1> Configure Ecache Limit 0,1>Ecache Size = 00100000, Limited to 00100000 0,1>Board 0 FPU Functional Test 0,1> FPU Enable 0,1>Board 0 Board Master Select Test 0,1> Selecting a Board Master 0,0> Ecache RAM 0,0> Ecache 6N RAM Pattern Test 0,0> Ecache Address Line 0,0> Configure Ecache Limit 0,0>Ecache Size = 00100000, Limited to 00100000 0,0>Board 0 FPU Functional Test 0,0> FPU Enable 0,0>Board 0 Board Master Select Test 0,0> Selecting a Board Master 0,0>Board 0 FireHose Devices Test 0,0> PROM Datapath Test 0,0> FHC CPU SRAM Test 0,0>Board 0 Address Controller Test 0,0> AC Registers Test 0,0> AC Initialization 0,0> Memory Registers Test 0,0> Memory Registers Initialization Test 0,0> AC DTAG Init 0,0>Board 0 Dual Tags Test 0,0> AC DTAG Test 0,0> AC DTAG Init 0,0>Board 0 FireHose Controller Test 0,0> FHC Initialization 0,0>Board 0 JTAG Test 0,0> Verify System Board Scan Ring 0,0>Board 0 Centerplane Test 0,0> Centerplane and Arbiter Check Test 0,0>Setting JTAG Master 0,0>Clear JTAG Master 0,0> Centerplane Join 0,0>Setting JTAG Master 0,0>Clear JTAG Master 0,0>Board 0 Setup Cache Size Test 0,0> Setting Up Cache Size 0,0>Board 0 System Master Select Test 0,0> Setting System Master 0,0>POST Master Selected (JTAG,CENTRAL) 0,0>Board 16 Clock Board Test 0,0> Clock Board Registers Test 0,0> Clock Board Initialization 0,0> Clock Board Temperature Check 0,0>Board 16 Clock Board Serial Ports Test 0,0> 85C30 Register Test 0,0> 85C30 Serial Ports Test 0,0>Keyboard Loopback 0,0>Mouse Loopback 0,0>Serial Port B Loopback 0,0>Remote Serial Port A Loopback 0,0>Remote Serial Port B Loopback 0,0>Board 16 NVRAM Devices Test 0,0> M48T59 (TOD) Init 0,0> M48T59 (TOD) Functional Part 1 Test 0,0> NVRAM(Non-Destructive) Test 0,0>Board 0 System Board Probe Test 0,0> Probing all CPU/Memory BDA 0,0> Probing System Boards 0,0> Probing CPU Module JTAG Rings 0,0>Setting System Clock Frequency 0,0>CPU Module mid 0 Checked in OK (speed code = 4) 0,0>CPU mid 1 Version=00170011.11000507 0,0>CPU Module mid 1 Checked in OK (speed code = 4) 0,0>CPU mid 8 Version=00170011.11000507 0,0>CPU Module mid 8 Checked in OK (speed code = 4) 0,0>CPU mid 9 Version=00170011.11000507 0,0>CPU Module mid 9 Checked in OK (speed code = 4) 0,0>CPU mid 10 Version=00170011.11000507 0,0>CPU Module mid 10 Checked in OK (speed code = 4) 0,0>CPU mid 11 Version=00170011.11000507 0,0>CPU Module mid 11 Checked in OK (speed code = 4) 0,0>CPU mid 12 Version=00170011.11000507 0,0>CPU Module mid 12 Checked in OK (speed code = 4) 0,0>CPU mid 13 Version=00170011.11000507 0,0>CPU Module mid 13 Checked in OK (speed code = 4) 0,0>CPU mid 14 Version=00170011.11000507 0,0>CPU Module mid 14 Checked in OK (speed code = 4) 0,0>CPU mid 15 Version=00170011.11000507 0,0>CPU Module mid 15 Checked in OK (speed code = 4) 0,0>CPU mid 16 Version=00170011.11000507 0,0>CPU Module mid 16 Checked in OK (speed code = 4) 0,0>CPU mid 17 Version=00170011.11000507 0,0>CPU Module mid 17 Checked in OK (speed code = 4) 0,0>CPU mid 18 Version=00170011.11000507 0,0>CPU Module mid 18 Checked in OK (speed code = 4) 0,0>CPU mid 19 Version=00170011.11000507 0,0>CPU Module mid 19 Checked in OK (speed code = 4) 0,0>CPU mid 22 Version=00170011.11000507 0,0>CPU Module mid 22 Checked in OK (speed code = 4) 0,0>CPU mid 23 Version=00170011.11000507 0,0>CPU Module mid 23 Checked in OK (speed code = 4) 0,0>System Frequency (MHz),fcpu=248, fmod=124, fsys=82, fgen=496 0,0>TESTING BOARD 1 0,0>Board 1 JTAG Test 0,0> Verify System Board Scan Ring 0,0>Board 1 Centerplane Test 0,0> Centerplane Check 0,0>Board 1 Address Controller Test 0,0> AC Registers Test 0,0> AC Initialization 0,0>Setting Freq to 25MHZ 0,0> Memory Registers Test 0,0> Memory Registers Initialization Test 0,0> AC DTAG Init 0,0>Board 1 FireHose Controller Test 0,0> FHC Initialization 0,0>Board 1 NVRAM Devices Test 0,0> M48T59 (TOD) Init 0,0> M48T59 (TOD) Functional Part 1 Test 0,0> NVRAM(Non-Destructive) Test 0,0>TESTING BOARD 2 0,0>Board 2 JTAG Test 0,0> Verify System Board Scan Ring 0,0>Board 2 Centerplane Test 0,0> Centerplane Check 0,0>Board 2 Address Controller Test 0,0> AC Registers Test 0,0> AC Initialization 0,0>Setting Freq to 25MHZ 0,0> Memory Registers Test 0,0> Memory Registers Initialization Test 0,0> AC DTAG Init 0,0>Board 2 FireHose Controller Test 0,0> FHC Initialization 0,0>Board 2 NVRAM Devices Test 0,0> M48T59 (TOD) Init 0,0> M48T59 (TOD) Functional Part 1 Test 0,0> NVRAM(Non-Destructive) Test 0,0>Re-mapping to Local Device Space 0,0>Begin Central Space Serial Port access 0,0>Enable AC Control Parity 0,0>Hotplug Trigger Test 0,0>Init Counters for Hotplug 0,0>Board 0 Cross Calls Test 0,0> Cross Calls Test 0,0>Displaying PROM Versions 0,0>Slot 0 CPU/Memory OBP 3.2.27 2000/8/18 11:15 POST 3.9.27 2000/8/18 11:19 0,0>Slot 1 IO Type 1 FCODE 1.8.27 2000/8/18 11:13 iPOST 3.4.27 2000/8/18 11:18 0,0>Slot 2 IO Type 1 FCODE 1.8.27 2000/8/18 11:13 iPOST 3.4.27 2000/8/18 11:18 0,0>Slot 4 CPU/Memory OBP 3.2.27 2000/8/18 11:15 POST 3.9.27 2000/8/18 11:19 0,0>Slot 5 CPU/Memory OBP 3.2.27 2000/8/18 11:15 POST 3.9.27 2000/8/18 11:19 0,0>Slot 6 CPU/Memory OBP 3.2.27 2000/8/18 11:15 POST 3.9.27 2000/8/18 11:19 0,0>Slot 7 CPU/Memory OBP 3.2.27 2000/8/18 11:15 POST 3.9.27 2000/8/18 11:19 0,0>Slot 8 CPU/Memory OBP 3.2.27 2000/8/18 11:15 POST 3.9.27 2000/8/18 11:19 0,0>Slot 9 CPU/Memory OBP 3.2.27 2000/8/18 11:15 POST 3.9.27 2000/8/18 11:19 0,0>Slot 11 CPU/Memory OBP 3.2.27 2000/8/18 11:15 POST 3.9.27 2000/8/18 11:19 0,0>Board 0 Environmental Probe Test 0,0> Environmental Probe 0,0>ERROR: TEST=Environmental Probe,SUBTEST=Environmental Probe ID=1f.1 0,0>Component under test: Board 0 System Interrupt 0,0>Rack Fan failed 0,0>Checking Power Supply Configuration 0,0>Power is more than adequate, load 10 ps 7 0,0> 0,0>System Environmental Status 0,0>----------------------------------------------------------------- 0,0> Slot Board Type Temp PS Stat Perph PS 0,0>----------------------------------------------------------------- 0,0> 0 | CPU/Memory | <28 | PS0 OK | PP0 OK | 0,0> 1 | IO Type 1 | <32 | PS1 OK | | 0,0> 2 | IO Type 1 | <32 | PS2 OK | | 0,0> 3 | Empty | | PS3 OK | | 0,0> 4 | CPU/Memory | <28 | PS4 OK | | 0,0> 5 | CPU/Memory | <28 | PS5 OK | | 0,0> 6 | CPU/Memory | <28 | PS6 N_PRES | | 0,0> 7 | CPU/Memory | <28 | PS7 OK | | 0,0> 8 | CPU/Memory | <28 | | | 0,0> 9 | CPU/Memory | <28 | | | 0,0> 10 | Empty | | | | 0,0> 11 | CPU/Memory | <24 | | | 0,0> 12 | Empty | | | | 0,0> 13 | Empty | | | | 0,0> 14 | Empty | | | | 0,0> 15 | Empty | | | | 0,0> 16 | Clock Board | <24 | | | 0,0>----------------------------------------------------------------- 0,0> 0,0>Precharge and Peripheral Power Supply Status 0,0>----------------------------------------------------------------- 0,0> V5_PCH V3_PCH V12_PCH V5_PPCH V5_AUX V12_P V5_P 0,0>----------------------------------------------------------------- 0,0> OK | OK | OK | OK | OK | OK | OK | 0,0>----------------------------------------------------------------- 0,0> 0,0>Miscellaneous Sensor Status 0,0>----------------------------------------------------------------- 0,0> RK_FAN AC_FAN KEY_FAN CLK_33 CLK_50 NOT_BD_PRES 0,0>----------------------------------------------------------------- 0,0> FAIL | OK | OK | OK | OK | ZERO | 0,0>----------------------------------------------------------------- 0,0>Reconfig memory due to POR or CLOCK RESET 0,0>Reconfig memory due to DIAG_LEVEL 0,0>Board 0 Probing Memory SIMMS Test 0,0> Probe SIMMID 0,0>Populated Memory Bank Status 0,0>bd #SizeAddressWayStatus 0,0>0256Normal 0,0>0256Normal 0,0>4256Normal 0,0>4256Normal 0,0>5256Normal 0,0>5256Normal 0,0>6256Normal 0,0>6256Normal 0,0>7256Normal 0,0>7256Normal 0,0>8256Normal 0,0>8256Normal 0,0>9256Normal 0,0>9256Normal 0,0>11256Normal 0,0>11256Normal 0,0>Board 0 Memory Configuration Test 0,0> Memory Interleaving 0,0>Total banks with 8MB SIMMs = 0 0,0>Total banks with 32MB SIMMs = 16 0,0>Total banks with 128MB SIMMs = 0 0,0>Total banks with 256MB SIMMs = 0 0,0>Overall memory default speed = 60ns 0,0>Do OPTIMAL INTLV 0,0>Board 0 AC rev 5 RCTIME = 0 (Tras 71) 0,0>Board 4 AC rev 5 RCTIME = 0 (Tras 71) 0,0>Board 5 AC rev 5 RCTIME = 0 (Tras 71) 0,0>Board 6 AC rev 5 RCTIME = 0 (Tras 71) 0,0>Board 7 AC rev 5 RCTIME = 0 (Tras 71) 0,0>Board 8 AC rev 5 RCTIME = 0 (Tras 71) 0,0>Board 9 AC rev 5 RCTIME = 0 (Tras 71) 0,0>Board 11 AC rev 5 RCTIME = 0 (Tras 71) 0,0>Board 0 AC rev 5 RCTIME = 0 (Tras 71) 0,0>Board 4 AC rev 5 RCTIME = 0 (Tras 71) 0,0>Board 5 AC rev 5 RCTIME = 0 (Tras 71) 0,0>Board 6 AC rev 5 RCTIME = 0 (Tras 71) 0,0>Board 7 AC rev 5 RCTIME = 0 (Tras 71) 0,0>Board 8 AC rev 5 RCTIME = 0 (Tras 71) 0,0>Board 9 AC rev 5 RCTIME = 0 (Tras 71) 0,0>Board 11 AC rev 5 RCTIME = 0 (Tras 71) 0,0> Memory Refresh Enable 0,0>Board 0 SIMMs Test 0,0> MP Memory SIMM Clear Test 0,0>Memory Size is 4096Mbytes 0,0> CPU MID 1 clearing 00000000.00004000 to 00000000.10000000 0,0> CPU MID 8 clearing 00000000.10000000 to 00000000.20000000 0,0> CPU MID 9 clearing 00000000.20000000 to 00000000.30000000 0,0> CPU MID 10 clearing 00000000.30000000 to 00000000.40000000 0,0> CPU MID 11 clearing 00000000.40000000 to 00000000.50000000 0,0> CPU MID 12 clearing 00000000.50000000 to 00000000.60000000 0,0> CPU MID 13 clearing 00000000.60000000 to 00000000.70000000 0,0> CPU MID 14 clearing 00000000.70000000 to 00000000.80000000 0,0> CPU MID 15 clearing 00000000.80000000 to 00000000.90000000 0,0> CPU MID 16 clearing 00000000.90000000 to 00000000.a0000000 0,0> CPU MID 17 clearing 00000000.a0000000 to 00000000.b0000000 0,0> CPU MID 18 clearing 00000000.b0000000 to 00000000.c0000000 0,0> CPU MID 19 clearing 00000000.c0000000 to 00000000.d0000000 0,0> CPU MID 22 clearing 00000000.d0000000 to 00000000.e0000000 0,0> CPU MID 23 clearing 00000000.e0000000 to 00000000.f0000000 0,0> CPU MID 0 clearing 00000000.f0000000 to 00000001.00000000 0,0> CPU MID 0 clearing 00000000.00000000 to 00000000.00004000 0,0> Memory Walking Rows and Columns Test 0,0> MP Memory SIMM (6N RAM Patterns) Test 0,0>Memory Size is 4096Mbytes 0,0> CPU MID 1 testing 00000000.00000000 to 00000000.15500000 0,0> CPU MID 8 testing 00000000.15500000 to 00000000.2aa00000 0,0> CPU MID 9 testing 00000000.2aa00000 to 00000000.3ff00000 0,0> CPU MID 10 testing 00000000.3ff00000 to 00000000.55400000 0,0> CPU MID 11 testing 00000000.55400000 to 00000000.6a900000 0,0> CPU MID 12 testing 00000000.6a900000 to 00000000.7fe00000 0,0> CPU MID 13 testing 00000000.7fe00000 to 00000000.95300000 0,0> CPU MID 14 testing 00000000.95300000 to 00000000.aa800000 0,0> CPU MID 15 testing 00000000.aa800000 to 00000000.bfd00000 0,0> CPU MID 16 testing 00000000.bfd00000 to 00000000.d5200000 0,0> CPU MID 17 testing 00000000.d5200000 to 00000000.ea700000 0,0> CPU MID 0 testing 00000000.ea700000 to 00000001.00000000 0,0> MP Memory SIMM (moving inverse) Test 0,0>Memory Size is 4096Mbytes 0,0> CPU MID 1 testing 00000000.00000000 to 00000000.15500000 0,0> CPU MID 8 testing 00000000.15500000 to 00000000.2aa00000 0,0> CPU MID 9 testing 00000000.2aa00000 to 00000000.3ff00000 0,0> CPU MID 10 testing 00000000.3ff00000 to 00000000.55400000 0,0> CPU MID 11 testing 00000000.55400000 to 00000000.6a900000 0,0> CPU MID 12 testing 00000000.6a900000 to 00000000.7fe00000 0,0> CPU MID 13 testing 00000000.7fe00000 to 00000000.95300000 0,0> CPU MID 14 testing 00000000.95300000 to 00000000.aa800000 0,0> CPU MID 15 testing 00000000.aa800000 to 00000000.bfd00000 0,0> CPU MID 16 testing 00000000.bfd00000 to 00000000.d5200000 0,0> CPU MID 17 testing 00000000.d5200000 to 00000000.ea700000 0,0> CPU MID 0 testing 00000000.ea700000 to 00000001.00000000 0,0>Slave CPU Functional Tests 0,0> Slave CPU MID 1 started 0,1>Board 0 Functional CPU 1 Test 0,1> Dcache Init 0,1> Dcache Enable Test 0,1> Dcache Functionality Test 0,1> Ecache Stress Test 0,1> Ecache Functional Test 0,1> CPU Dispatch (Multi-Scalar) Test 0,1> SPARC Atomic Instructions Test 0,1> SPARC Prefetch Instructions Test 0,1> CPU Softint Registers and Interrupts Test 0,1> Uni-Processor Cache Coherence Test 0,1> Branch Memory Test 0,1> SDB ECC CE Test 0,1> SDB ECC Uncorrectable Test 0,1> FPU Instruction Test 0,0> Slave CPU MID 8 started 4,0>Board 4 Functional CPU 0 Test 4,0> Dcache Init 4,0> Dcache Enable Test 4,0> Dcache Functionality Test 4,0> Ecache Stress Test 4,0> Ecache Functional Test 4,0> CPU Dispatch (Multi-Scalar) Test 4,0> SPARC Atomic Instructions Test 4,0> SPARC Prefetch Instructions Test 4,0> CPU Softint Registers and Interrupts Test 4,0> Uni-Processor Cache Coherence Test 4,0> Branch Memory Test 4,0> SDB ECC CE Test 4,0> SDB ECC Uncorrectable Test 4,0> FPU Instruction Test 0,0> Slave CPU MID 9 started 4,1>Board 4 Functional CPU 1 Test 4,1> Dcache Init 4,1> Dcache Enable Test 4,1> Dcache Functionality Test 4,1> Ecache Stress Test 4,1> Ecache Functional Test 4,1> CPU Dispatch (Multi-Scalar) Test 4,1> SPARC Atomic Instructions Test 4,1> SPARC Prefetch Instructions Test 4,1> CPU Softint Registers and Interrupts Test 4,1> Uni-Processor Cache Coherence Test 4,1> Branch Memory Test 4,1> SDB ECC CE Test 4,1> SDB ECC Uncorrectable Test 4,1> FPU Instruction Test 0,0> Slave CPU MID 10 started 5,0>Board 5 Functional CPU 0 Test 5,0> Dcache Init 5,0> Dcache Enable Test 5,0> Dcache Functionality Test 5,0> Ecache Stress Test 5,0> Ecache Functional Test 5,0> CPU Dispatch (Multi-Scalar) Test 5,0> SPARC Atomic Instructions Test 5,0> SPARC Prefetch Instructions Test 5,0> CPU Softint Registers and Interrupts Test 5,0> Uni-Processor Cache Coherence Test 5,0> Branch Memory Test 5,0> SDB ECC CE Test 5,0> SDB ECC Uncorrectable Test 5,0> FPU Instruction Test 0,0> Slave CPU MID 11 started 5,1>Board 5 Functional CPU 1 Test 5,1> Dcache Init 5,1> Dcache Enable Test 5,1> Dcache Functionality Test 5,1> Ecache Stress Test 5,1> Ecache Functional Test 5,1> CPU Dispatch (Multi-Scalar) Test 5,1> SPARC Atomic Instructions Test 5,1> SPARC Prefetch Instructions Test 5,1> CPU Softint Registers and Interrupts Test 5,1> Uni-Processor Cache Coherence Test 5,1> Branch Memory Test 5,1> SDB ECC CE Test 5,1> SDB ECC Uncorrectable Test 5,1> FPU Instruction Test 0,0> Slave CPU MID 12 started 6,0>Board 6 Functional CPU 0 Test 6,0> Dcache Init 6,0> Dcache Enable Test 6,0> Dcache Functionality Test 6,0> Ecache Stress Test 6,0> Ecache Functional Test 6,0> CPU Dispatch (Multi-Scalar) Test 6,0> SPARC Atomic Instructions Test 6,0> SPARC Prefetch Instructions Test 6,0> CPU Softint Registers and Interrupts Test 6,0> Uni-Processor Cache Coherence Test 6,0> Branch Memory Test 6,0> SDB ECC CE Test 6,0> SDB ECC Uncorrectable Test 6,0> FPU Instruction Test 0,0> Slave CPU MID 13 started 6,1>Board 6 Functional CPU 1 Test 6,1> Dcache Init 6,1> Dcache Enable Test 6,1> Dcache Functionality Test 6,1> Ecache Stress Test 6,1> Ecache Functional Test 6,1> CPU Dispatch (Multi-Scalar) Test 6,1> SPARC Atomic Instructions Test 6,1> SPARC Prefetch Instructions Test 6,1> CPU Softint Registers and Interrupts Test 6,1> Uni-Processor Cache Coherence Test 6,1> Branch Memory Test 6,1> SDB ECC CE Test 6,1> SDB ECC Uncorrectable Test 6,1> FPU Instruction Test 0,0> Slave CPU MID 14 started 7,0>Board 7 Functional CPU 0 Test 7,0> Dcache Init 7,0> Dcache Enable Test 7,0> Dcache Functionality Test 7,0> Ecache Stress Test 7,0> Ecache Functional Test 7,0> CPU Dispatch (Multi-Scalar) Test 7,0> SPARC Atomic Instructions Test 7,0> SPARC Prefetch Instructions Test 7,0> CPU Softint Registers and Interrupts Test 7,0> Uni-Processor Cache Coherence Test 7,0> Branch Memory Test 7,0> SDB ECC CE Test 7,0> SDB ECC Uncorrectable Test 7,0> FPU Instruction Test 0,0> Slave CPU MID 15 started 7,1>Board 7 Functional CPU 1 Test 7,1> Dcache Init 7,1> Dcache Enable Test 7,1> Dcache Functionality Test 7,1> Ecache Stress Test 7,1> Ecache Functional Test 7,1> CPU Dispatch (Multi-Scalar) Test 7,1> SPARC Atomic Instructions Test 7,1> SPARC Prefetch Instructions Test 7,1> CPU Softint Registers and Interrupts Test 7,1> Uni-Processor Cache Coherence Test 7,1> Branch Memory Test 7,1> SDB ECC CE Test 7,1> SDB ECC Uncorrectable Test 7,1> FPU Instruction Test 0,0> Slave CPU MID 16 started 8,0>Board 8 Functional CPU 0 Test 8,0> Dcache Init 8,0> Dcache Enable Test 8,0> Dcache Functionality Test 8,0> Ecache Stress Test 8,0> Ecache Functional Test 8,0> CPU Dispatch (Multi-Scalar) Test 8,0> SPARC Atomic Instructions Test 8,0> SPARC Prefetch Instructions Test 8,0> CPU Softint Registers and Interrupts Test 8,0> Uni-Processor Cache Coherence Test 8,0> Branch Memory Test 8,0> SDB ECC CE Test 8,0> SDB ECC Uncorrectable Test 8,0> FPU Instruction Test 0,0> Slave CPU MID 17 started 8,1>Board 8 Functional CPU 1 Test 8,1> Dcache Init 8,1> Dcache Enable Test 8,1> Dcache Functionality Test 8,1> Ecache Stress Test 8,1> Ecache Functional Test 8,1> CPU Dispatch (Multi-Scalar) Test 8,1> SPARC Atomic Instructions Test 8,1> SPARC Prefetch Instructions Test 8,1> CPU Softint Registers and Interrupts Test 8,1> Uni-Processor Cache Coherence Test 8,1> Branch Memory Test 8,1> SDB ECC CE Test 8,1> SDB ECC Uncorrectable Test 8,1> FPU Instruction Test 0,0> Slave CPU MID 18 started 9,0>Board 9 Functional CPU 0 Test 9,0> Dcache Init 9,0> Dcache Enable Test 9,0> Dcache Functionality Test 9,0> Ecache Stress Test 9,0> Ecache Functional Test 9,0> CPU Dispatch (Multi-Scalar) Test 9,0> SPARC Atomic Instructions Test 9,0> SPARC Prefetch Instructions Test 9,0> CPU Softint Registers and Interrupts Test 9,0> Uni-Processor Cache Coherence Test 9,0> Branch Memory Test 9,0> SDB ECC CE Test 9,0> SDB ECC Uncorrectable Test 9,0> FPU Instruction Test 0,0> Slave CPU MID 19 started 9,1>Board 9 Functional CPU 1 Test 9,1> Dcache Init 9,1> Dcache Enable Test 9,1> Dcache Functionality Test 9,1> Ecache Stress Test 9,1> Ecache Functional Test 9,1> CPU Dispatch (Multi-Scalar) Test 9,1> SPARC Atomic Instructions Test 9,1> SPARC Prefetch Instructions Test 9,1> CPU Softint Registers and Interrupts Test 9,1> Uni-Processor Cache Coherence Test 9,1> Branch Memory Test 9,1> SDB ECC CE Test 9,1> SDB ECC Uncorrectable Test 9,1> FPU Instruction Test 0,0> Slave CPU MID 22 started 11,0>Board 11 Functional CPU 0 Test 11,0> Dcache Init 11,0> Dcache Enable Test 11,0> Dcache Functionality Test 11,0> Ecache Stress Test 11,0> Ecache Functional Test 11,0> CPU Dispatch (Multi-Scalar) Test 11,0> SPARC Atomic Instructions Test 11,0> SPARC Prefetch Instructions Test 11,0> CPU Softint Registers and Interrupts Test 11,0> Uni-Processor Cache Coherence Test 11,0> Branch Memory Test 11,0> SDB ECC CE Test 11,0> SDB ECC Uncorrectable Test 11,0> FPU Instruction Test 0,0> Slave CPU MID 23 started 11,1>Board 11 Functional CPU 1 Test 11,1> Dcache Init 11,1> Dcache Enable Test 11,1> Dcache Functionality Test 11,1> Ecache Stress Test 11,1> Ecache Functional Test 11,1> CPU Dispatch (Multi-Scalar) Test 11,1> SPARC Atomic Instructions Test 11,1> SPARC Prefetch Instructions Test 11,1> CPU Softint Registers and Interrupts Test 11,1> Uni-Processor Cache Coherence Test 11,1> Branch Memory Test 11,1> SDB ECC CE Test 11,1> SDB ECC Uncorrectable Test 11,1> FPU Instruction Test 0,0>Board 0 Functional CPU 0 Test 0,0> Dcache Init 0,0> Dcache Enable Test 0,0> Dcache Functionality Test 0,0> Ecache Stress Test 0,0> Ecache Functional Test 0,0> CPU Dispatch (Multi-Scalar) Test 0,0> SPARC Atomic Instructions Test 0,0> SPARC Prefetch Instructions Test 0,0> CPU Softint Registers and Interrupts Test 0,0> Uni-Processor Cache Coherence Test 0,0> Branch Memory Test 0,0> SDB ECC CE Test 0,0> SDB ECC Uncorrectable Test 0,0> FPU Instruction Test 0,0>TESTING IO BOARD 1 0,0>Board 1 I/O FPROM Test 0,0> I/O Board EPROM checksum Test 0,0>@(#) iPOST 3.4.27 2000/08/18 11:18 0,0> TESTING IO BOARD 1 ASICs 0,0> TESTING SysIO Port 0 0,0>Board 1 SysIO Registers Test 0,0> SysIO Register Initialization 0,0> IOMMU Registers and RAM Test 0,0> Streaming Buffer Registers and RAM Test 0,0> SBus Control and Config Registers Test 0,0> SysIO RAM Initialization 0,0>Board 1 SysIO Functional Test 0,0> Clear Interrupt Map and State Registers 0,0> SysIO Interrupts Test 0,0> SysIO Timers/Counters Test 0,0> IOMMU Virtual Address TLB Tag Compare Test 0,0> Streaming Buffer Flush Test 0,0> DMA Merge Buffer Test 0,0> SYSIO ECC Correctable Test 0,0> SYSIO ECC UnCorrectable Test 0,0> SysIO Sbus Probe Test 0,0>Sbus Card Installed, slot #1, addr 000001c5.10000000 0,0>Sbus Card Installed, slot #2, addr 000001c5.20000000 0,0> SysIO Register Initialization Test 0,0> SysIO RAM Initialization Test 0,0> Clear Interrupt Map and State Registers Test 0,0>Board 1 OnBoard IO Chipset (SOC) Test 0,0> SOC SRAM Test 0,0> SOC Registers Test 0,0> SOC Interrupt Test 0,0> Clear Interrupt Map and State Registers Test 0,0> TESTING SysIO Port 1 0,0>Board 1 SysIO Registers Test 0,0> SysIO Register Initialization 0,0> IOMMU Registers and RAM Test 0,0> Streaming Buffer Registers and RAM Test 0,0> SBus Control and Config Registers Test 0,0> SysIO RAM Initialization 0,0>Board 1 SysIO Functional Test 0,0> Clear Interrupt Map and State Registers 0,0> SysIO Interrupts Test 0,0> SysIO Timers/Counters Test 0,0> IOMMU Virtual Address TLB Tag Compare Test 0,0> Streaming Buffer Flush Test 0,0> DMA Merge Buffer Test 0,0> SYSIO ECC Correctable Test 0,0> SYSIO ECC UnCorrectable Test 0,0> SysIO Sbus Probe Test 0,0>SBus Card not Installed, slot 0 addr 000001c7.00000000 0,0> SysIO Register Initialization Test 0,0> SysIO RAM Initialization Test 0,0> Clear Interrupt Map and State Registers Test 0,0>Board 1 OnBoard IO Chipset (FEPS) Test 0,0> FAS366 Registers Test 0,0> ESP FAS366 DVMA burst mode read/write Test 0,0> FAS366 FIFO TO DMA Test 0,0> DMA TO FAS366 FIFO Test 0,0> FEPS (Ethernet) Registers Test 0,0> FEPS Ethernet(BM, DP83840, Twister) Internal Loopbacks Test 0,0> SysIO Register Initialization Test 0,0> SysIO RAM Initialization Test 0,0> Clear Interrupt Map and State Registers Test 0,0>IO BOARD 1 TESTED 0,0>TESTING IO BOARD 2 0,0>Board 2 I/O FPROM Test 0,0> I/O Board EPROM checksum Test 0,0>@(#) iPOST 3.4.27 2000/08/18 11:18 0,0> TESTING IO BOARD 2 ASICs 0,0> TESTING SysIO Port 0 0,0>Board 2 SysIO Registers Test 0,0> SysIO Register Initialization 0,0> IOMMU Registers and RAM Test 0,0> Streaming Buffer Registers and RAM Test 0,0> SBus Control and Config Registers Test 0,0> SysIO RAM Initialization 0,0>Board 2 SysIO Functional Test 0,0> Clear Interrupt Map and State Registers 0,0> SysIO Interrupts Test 0,0> SysIO Timers/Counters Test 0,0> IOMMU Virtual Address TLB Tag Compare Test 0,0> Streaming Buffer Flush Test 0,0> DMA Merge Buffer Test 0,0> SYSIO ECC Correctable Test 0,0> SYSIO ECC UnCorrectable Test 0,0> SysIO Sbus Probe Test 0,0>Sbus Card Installed, slot #1, addr 000001c9.10000000 0,0>Sbus Card Installed, slot #2, addr 000001c9.20000000 0,0> SysIO Register Initialization Test 0,0> SysIO RAM Initialization Test 0,0> Clear Interrupt Map and State Registers Test 0,0>Board 2 OnBoard IO Chipset (SOC) Test 0,0> SOC SRAM Test 0,0> SOC Registers Test 0,0> SOC Interrupt Test 0,0> Clear Interrupt Map and State Registers Test 0,0> TESTING SysIO Port 1 0,0>Board 2 SysIO Registers Test 0,0> SysIO Register Initialization 0,0> IOMMU Registers and RAM Test 0,0> Streaming Buffer Registers and RAM Test 0,0> SBus Control and Config Registers Test 0,0> SysIO RAM Initialization 0,0>Board 2 SysIO Functional Test 0,0> Clear Interrupt Map and State Registers 0,0> SysIO Interrupts Test 0,0> SysIO Timers/Counters Test 0,0> IOMMU Virtual Address TLB Tag Compare Test 0,0> Streaming Buffer Flush Test 0,0> DMA Merge Buffer Test 0,0> SYSIO ECC Correctable Test 0,0> SYSIO ECC UnCorrectable Test 0,0> SysIO Sbus Probe Test 0,0>Sbus Card Installed, slot #0, addr 000001cb.00000000 0,0> SysIO Register Initialization Test 0,0> SysIO RAM Initialization Test 0,0> Clear Interrupt Map and State Registers Test 0,0>Board 2 OnBoard IO Chipset (FEPS) Test 0,0> FAS366 Registers Test 0,0> ESP FAS366 DVMA burst mode read/write Test 0,0> FAS366 FIFO TO DMA Test 0,0> DMA TO FAS366 FIFO Test 0,0> FEPS (Ethernet) Registers Test 0,0> FEPS Ethernet(BM, DP83840, Twister) Internal Loopbacks Test 0,0> SysIO Register Initialization Test 0,0> SysIO RAM Initialization Test 0,0> Clear Interrupt Map and State Registers Test 0,0>IO BOARD 2 TESTED 0,0>SYSTEM LEVEL TESTING 0,0>Board 0 Cache Coherency Test 0,0> Multi-Processor Cache Coherence Test 0,0>Testing CPU MID 1 0,0>Testing CPU MID 8 0,0>Testing CPU MID 9 0,0>Testing CPU MID 10 0,0>Testing CPU MID 11 0,0>Testing CPU MID 12 0,0>Testing CPU MID 13 0,0>Testing CPU MID 14 0,0>Testing CPU MID 15 0,0>Testing CPU MID 16 0,0>Testing CPU MID 17 0,0>Testing CPU MID 18 0,0>Testing CPU MID 19 0,0>Testing CPU MID 22 0,0>Testing CPU MID 23 0,0>Probing for Disk System boards 0,0>Board 0 System Interrupts Test 0,0> System Interrupts Test 0,0>ERROR: TEST=System Interrupts,SUBTEST=System Interrupts ID=1f.1 0,0>Component under test: Board 0 System Interrupt 0,0>Rack Fan failed 0,0>Checking Power Supply Configuration 0,0>Power is more than adequate, load 10 ps 7 0,0> 0,0>System Environmental Status 0,0>----------------------------------------------------------------- 0,0> Slot Board Type Temp PS Stat Perph PS 0,0>----------------------------------------------------------------- 0,0> 0 | CPU/Memory | <33 | PS0 OK | PP0 OK | 0,0> 1 | IO Type 1 | <32 | PS1 OK | | 0,0> 2 | IO Type 1 | <32 | PS2 OK | | 0,0> 3 | Empty | | PS3 OK | | 0,0> 4 | CPU/Memory | <33 | PS4 OK | | 0,0> 5 | CPU/Memory | <33 | PS5 OK | | 0,0> 6 | CPU/Memory | <33 | PS6 N_PRES | | 0,0> 7 | CPU/Memory | <33 | PS7 OK | | 0,0> 8 | CPU/Memory | <28 | | | 0,0> 9 | CPU/Memory | <33 | | | 0,0> 10 | Empty | | | | 0,0> 11 | CPU/Memory | <28 | | | 0,0> 12 | Empty | | | | 0,0> 13 | Empty | | | | 0,0> 14 | Empty | | | | 0,0> 15 | Empty | | | | 0,0> 16 | Clock Board | <24 | | | 0,0>----------------------------------------------------------------- 0,0> 0,0>Precharge and Peripheral Power Supply Status 0,0>----------------------------------------------------------------- 0,0> V5_PCH V3_PCH V12_PCH V5_PPCH V5_AUX V12_P V5_P 0,0>----------------------------------------------------------------- 0,0> OK | OK | OK | OK | OK | OK | OK | 0,0>----------------------------------------------------------------- 0,0> 0,0>Miscellaneous Sensor Status 0,0>----------------------------------------------------------------- 0,0> RK_FAN AC_FAN KEY_FAN CLK_33 CLK_50 NOT_BD_PRES 0,0>----------------------------------------------------------------- 0,0> FAIL | OK | OK | OK | OK | ONE | 0,0>----------------------------------------------------------------- 0,0>WARNING Test skipped, Interrupts Pending 0,0> Check Board Present Test 0,0> Board Present Interrupt Test 0,0>POST Failed 0,0> 0,0>System Board Status 0,0>----------------------------------------------------------------- 0,0> Slot Board Status Board Type Failures 0,0>----------------------------------------------------------------- 0,0> 0 | Normal | CPU/Memory | 0,0> 1 | Normal | IO Type 1 | 0,0> 2 | Normal | IO Type 1 | 0,0> 3 | Normal | Disk Board | 0,0> 4 | Normal | CPU/Memory | 0,0> 5 | Normal | CPU/Memory | 0,0> 6 | Normal | CPU/Memory | 0,0> 7 | Normal | CPU/Memory | 0,0> 8 | Normal | CPU/Memory | 0,0> 9 | Normal | CPU/Memory | 0,0> 10 | Not installed | | 0,0> 11 | Normal | CPU/Memory | 0,0> 12 | Not installed | | 0,0> 13 | Not installed | | 0,0> 14 | Not installed | | 0,0> 15 | Not installed | | 0,0> 16 | Online/failure | Clock Board | RACK_FAN_FAIL 0,0>----------------------------------------------------------------- 0,0> 0,0>CPU Module Status 0,0>----------------------------------------------------------------- 0,0> MID OK Cache Speed Version 0,0>----------------------------------------------------------------- 0,0> 0 | y | 1024 | 248 | 00170011.11000507 0,0> 1 | y | 1024 | 248 | 00170011.11000507 0,0> 8 | y | 1024 | 248 | 00170011.11000507 0,0> 9 | y | 1024 | 248 | 00170011.11000507 0,0> 10 | y | 1024 | 248 | 00170011.11000507 0,0> 11 | y | 1024 | 248 | 00170011.11000507 0,0> 12 | y | 1024 | 248 | 00170011.11000507 0,0> 13 | y | 1024 | 248 | 00170011.11000507 0,0> 14 | y | 1024 | 248 | 00170011.11000507 0,0> 15 | y | 1024 | 248 | 00170011.11000507 0,0> 16 | y | 1024 | 248 | 00170011.11000507 0,0> 17 | y | 1024 | 248 | 00170011.11000507 0,0> 18 | y | 1024 | 248 | 00170011.11000507 0,0> 19 | y | 1024 | 248 | 00170011.11000507 0,0> 22 | y | 1024 | 248 | 00170011.11000507 0,0> 23 | y | 1024 | 248 | 00170011.11000507 0,0>----------------------------------------------------------------- 0,0>System Frequency (MHz),fcpu=248, fmod=124, fsys=82, fgen=496 0,0>Populated Memory Bank Status 0,0>bd #SizeAddressWayStatus 0,0>0256016Normal 0,0>0256816Normal 0,0>4256116Normal 0,0>4256916Normal 0,0>5256216Normal 0,0>5256a16Normal 0,0>6256316Normal 0,0>6256b16Normal 0,0>7256416Normal 0,0>7256c16Normal 0,0>8256516Normal 0,0>8256d16Normal 0,0>9256616Normal 0,0>9256e16Normal 0,0>11256716Normal 0,0>11256f16Normal 0,0> 0,0>Disk Board Status 0,0>----------------------------------------------------------------- 0,0>Slot Sckt0 Sckt1 0,0>----------------------------------------------------------------- 0,0> 3 Disk10 Disk11 0,0> 0,0> 0,0> POST COMPLETE 0,0>Entering OBP ttya initialized Using POST's System Configuration Setting up memory Starting CPU ID 1 Starting CPU ID 8 Starting CPU ID 9 Starting CPU ID 10 Starting CPU ID 11 Starting CPU ID 12 Starting CPU ID 13 Starting CPU ID 14 Starting CPU ID 15 Starting CPU ID 16 Starting CPU ID 17 Starting CPU ID 18 Starting CPU ID 19 Starting CPU ID 22 Starting CPU ID 23 fhc ac simm-status environment sram flashprom SUNW,UltraSPARC-II SUNW,UltraSPARC-II fhc ac simm-status environment sram flashprom SUNW,UltraSPARC-II SUNW,UltraSPARC-II fhc ac simm-status environment sram flashprom SUNW,UltraSPARC-II SUNW,UltraSPARC-II fhc ac simm-status environment sram flashprom SUNW,UltraSPARC-II SUNW,UltraSPARC-II fhc ac simm-status environment sram flashprom SUNW,UltraSPARC-II SUNW,UltraSPARC-II fhc ac simm-status environment sram flashprom SUNW,UltraSPARC-II SUNW,UltraSPARC-II fhc ac simm-status environment sram flashprom SUNW,UltraSPARC-II SUNW,UltraSPARC-II fhc ac simm-status environment sram flashprom SUNW,UltraSPARC-II SUNW,UltraSPARC-II disk-board Probing UPA Slot at 2,0 sbus fhc ac environment flashprom eeprom sbus-speed counter-timer Probing UPA Slot at 3,0 sbus counter-timer Probing UPA Slot at 4,0 sbus fhc ac environment flashprom eeprom sbus-speed counter-timer Probing UPA Slot at 5,0 sbus counter-timer Probing /sbus@2,0 at d,0 SUNW,soc Probing /sbus@2,0 at 1,0 cgsix Probing /sbus@2,0 at 2,0 dma esp sd st lebuffer le Probing /sbus@3,0 at 3,0 SUNW,hme SUNW,fas sd st Probing /sbus@3,0 at 0,0 Nothing there Probing /sbus@4,0 at d,0 SUNW,soc Probing /sbus@4,0 at 1,0 network Probing /sbus@4,0 at 2,0 SUNW,soc Probing /sbus@5,0 at 3,0 SUNW,hme SUNW,fas sd st Probing /sbus@5,0 at 0,0 SUNW,qfe SUNW,qfe SUNW,qfe SUNW,qfe Using POST's System Configuration Setting up memory Starting CPU ID 1 Starting CPU ID 8 Starting CPU ID 9 Starting CPU ID 10 Starting CPU ID 11 Starting CPU ID 12 Starting CPU ID 13 Starting CPU ID 14 Starting CPU ID 15 Starting CPU ID 16 Starting CPU ID 17 Starting CPU ID 18 Starting CPU ID 19 Starting CPU ID 22 Starting CPU ID 23 fhc ac simm-status environment sram flashprom SUNW,UltraSPARC-II SUNW,UltraSPARC-II fhc ac simm-status environment sram flashprom SUNW,UltraSPARC-II SUNW,UltraSPARC-II fhc ac simm-status environment sram flashprom SUNW,UltraSPARC-II SUNW,UltraSPARC-II fhc ac simm-status environment sram flashprom SUNW,UltraSPARC-II SUNW,UltraSPARC-II fhc ac simm-status environment sram flashprom SUNW,UltraSPARC-II SUNW,UltraSPARC-II fhc ac simm-status environment sram flashprom SUNW,UltraSPARC-II SUNW,UltraSPARC-II fhc ac simm-status environment sram flashprom SUNW,UltraSPARC-II SUNW,UltraSPARC-II fhc ac simm-status environment sram flashprom SUNW,UltraSPARC-II SUNW,UltraSPARC-II disk-board Probing UPA Slot at 2,0 sbus fhc ac environment flashprom eeprom sbus-speed counter-timer Probing UPA Slot at 3,0 sbus counter-timer Probing UPA Slot at 4,0 sbus fhc ac environment flashprom eeprom sbus-speed counter-timer Probing UPA Slot at 5,0 sbus counter-timer Probing /sbus@2,0 at d,0 SUNW,soc Probing /sbus@2,0 at 1,0 cgsix Probing /sbus@2,0 at 2,0 dma esp sd st lebuffer le Probing /sbus@3,0 at 3,0 SUNW,hme SUNW,fas sd st Probing /sbus@3,0 at 0,0 Nothing there Probing /sbus@4,0 at d,0 SUNW,soc Probing /sbus@4,0 at 1,0 network Probing /sbus@4,0 at 2,0 SUNW,soc Probing /sbus@5,0 at 3,0 SUNW,hme SUNW,fas sd st Probing /sbus@5,0 at 0,0 SUNW,qfe SUNW,qfe SUNW,qfe SUNW,qfe 16-slot Sun Enterprise 6000, No Keyboard OpenBoot 3.2.27, 4096 MB memory installed, Serial #7259420. Copyright 2000 Sun Microsystems, Inc. All rights reserved Ethernet address 8:0:20:88:f:2b, Host ID: 806ec51c. {0} ok boot diskbrd-alt Boot device: /sbus@3,0/SUNW,fas@3,8800000/sd@b,0 File and args: Loading ufs-file-system package 1.4 04 Aug 1995 13:02:54. FCode UFS Reader 1.10 96/10/15 00:57:29. Loading: /platform/SUNW,Ultra-Enterprise/ufsboot Loading: /platform/sun4u/ufsboot SunOS Release 5.6 Version Generic_105181-39 [UNIX(R) System V Release 4.0] Copyright (c) 1983-2003, Sun Microsystems, Inc. WARNING: Rack Exhaust fan failure detected configuring network interfaces: hme0. Hostname: e6000 The / file system (/dev/rdsk/c0t11d0s0) is being checked. /dev/rdsk/c0t11d0s0: 34520 files, 565341 used, 1418921 free /dev/rdsk/c0t11d0s0: (2393 frags, 177066 blocks, 0.1% fragmentation) The system is coming up. Please wait. add net default: gateway 192.168.16.254 starting rpc services: rpcbind keyserv done. Setting default interface for multicast: add net 224.0.0.0: gateway e6000 syslog service starting. Print services started. /dev/bd.off: not a serial device. bdconfig: no serial device configured. Run bdconfig interactively (no args). volume management starting. The system is ready. e6000 console login: ***************************************************************************** * * Starting Desktop Login on display :0... * * Wait for the Desktop Login screen before logging in. * ***************************************************************************** Nov 6 18:21:52 e6000 sendmail[189]: My unqualified host name (e6000) unknown; sleeping for retry e6000 console login: root Password: Nov 6 18:22:15 e6000 login: ROOT LOGIN /dev/console Last login: Wed Nov 6 00:43:14 from :0 Sun Microsystems Inc. SunOS 5.6 Generic August 1997 # df -kl Filesystem kbytes used avail capacity Mounted on /dev/dsk/c0t11d0s0 1984262 565351 1359384 30% / /proc 0 0 0 0% /proc fd 0 0 0 0% /dev/fd swap 3491552 8 3491544 1% /tmp # uname -a SunOS e6000 5.6 Generic_105181-39 sun4u sparc SUNW,Ultra-Enterprise # init 0 INIT: New run level: 0 The system is coming down. Please wait. System services are now being stopped. Print services stopped. Stopping the syslog service. Nov 6 18:22:53 e6000 syslogd: going down on signal 15 nfs umount: /vol: not mounted Nov 6 18:22:54 snmpdx: received signal 15 The system is down. syncing file systems... done Program terminated {f} ok